Online Model Swapping in Architectural Simulation
Advisors: Prof. Richard Vuduc and Dr. Jeffrey Young
As systems grow more complex, detailed simulation takes an ever increasing amount of time. Likewise, real applications of interest often evolve faster than representative micro-benchmarks (e.g. machine learning), driving a need for real one-shot online simulation techniques that enable reasonable workload execution within the simulated environment. The prospect of increased simulation time and subsequent slower design iteration forces architects to use simpler models (e.g. spreadsheets) when they want to iterate quickly on a design. However, the task of migrating from a simple simulation to one with more detail often requires multiple executions to find where simple models could be effective, which could be more expensive than running the detailed model. With looming product and paper deadlines, many architects rely not on detailed model comparison but on intuition to select simple models. Our work, however, could allow architects to close this modeling control flow loop, reducing overall simulation time while enabling automation to make principled decisions as to when to select a simpler model.
In this work, we present a method of bridging the gap between simple and detailed simulation by monitoring simulation behavior online, and automatically swapping out detailed models with simpler statistical approximations when possible. We demonstrate the potential of our methodology as a proof of concept by implementing it in the open-source simulator SVE-Cachesim. Specifically we show that we can swap out the level one data cache (L1D) within a memory hierarchy. This demonstrates that our technique can handle a non-trivial use-case involving not just approximation of local time-invariant statistics, but also those that vary with time (e.g. the L1D is a form of a time-series function), and downstream side-effects (e.g. the L1D filters accesses for the level two cache). Our simulation swaps out the built-in cache model with only an 8% error in the simulated cycle count while using the approximated cache models for over 90% of the simulation, and our simpler models require two to eight times less computation per "execution" of the model.
Patrick Lavin is a fifth year PhD student at Georgia Tech with a research focus on performance modeling and system characterization. As the primary developer of the Spatter benchmark suite, he has been investigating indexed and irregular memory access patterns in HPC applications and how to properly characterize both CPU and GPU systems using gather/scatter operations. Recently, he has also spent time working on accelerating architectural simulation. Patrick is advised by Dr. Richard Vuduc, a professor in the School of Computational Science and Engineering at Georgia Tech and Dr. Jeffrey Young, a research scientist in the School of Computer Science.